soc-design

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Education kit for teaching introductory Arm-based system-on-chip design on FPGA with lectures and practical labs (educational)

Education kit for teaching advanced Arm Cortex-A system-on-chip design on FPGA platforms with lectures and hands-on labs (educational)

Textbook for advanced students and engineers on modern SoC design using Arm Cortex-A: architecture, interconnects, validation, and fabrication (educational)

Reference book for SoC and FPGA designers integrating Arm Cortex-M processors with AMBA bus architectures (educational)

⚙️ 基于 Zynq-7 全可编程 SoC 的设计

BDD Gherkin implementation in native SystemVerilog, based on UVM.

Open-source Non-coherent CHI Bridge (CHI SN-F to AXI-4 bridge)

SystemVerilog implementation of a multi-bank memory as part of "[F23] Digital Circuit Design" course

A reusable OpenClaw agent squad for chip architecture, RTL, DV, STA, PD, DFT, analog, and layout collaboration.

Entries for the 2023 5th National College Student Integrated Circuit EDA Elite Challenge. SoC chip physical layout static IR drop prediction project based on methods such as image processing and NLP unsupervised learning.

Humans respond more to **relative change (difference)** and **events (extrema/saturation)** than absolute levels. TFSDxr‑Neuron‑Quantization [TimeFeedBackSigmaDelta 4 eXtensible Reality] maps this principle into digital logic for **low‑power, event‑based encoding**.

Digital VLSI Soc-Physical Design (Picorv32)

SoCeteer - A framework for designing and running RISC-V-based SoCs on FPGA and in Simulation, built on top of Chisel.

End-to-end ASIC SoC design and functional verification of a lightweight machine learning accelerator using SystemVerilog and UVM. Includes Python automation for test generation and result analysis. Built to simulate real-world ML silicon validation at scale.

Personal GitHub profile — Embedded Systems, FPGA/SoC design, and hardware security engineer.

Semiconductor insights from technology trends, industry structure, and product evolution. （技術トレンド・産業構造・製品進化の視点から半導体を俯瞰する）

Hardware image processing system on DE1-SoC (Cyclone V FPGA + Nios II) featuring SDRAM frame buffering, RGB565 image display, real-time RGB-to-RGB565 decoding, Grayscale, Sobel Edge Detection, Sharpen filtering, and VGA output at 640×480 @ 60Hz.

A complete 1×3 NoC router implemented from RTL to GDSII using the Sky130A PDK. Includes full functional verification, synthesis (Yosys), and physical design using OpenLane/OpenROAD, culminating in a signoff-clean GDS layout.